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Join us in reinventing general-purpose processors

Ascenium is looking for experienced team members that want to contribute to

the creation of something really great - a processor creation effort unlike anything 

else they have ever worked on.

You know who you are and you know what skillsets are required to build a

high performance state-of-the-art microprocessor.

If you know what we are working on from our open source efforts and are interested taking part, don't be a stranger. Reach out to us on LinkedIn for a virtual coffee (
+47 47 38 06 34, or

View positions and apply

What do we do?

We design the next-generation data center CPU. That's right! We challenge Intel's x86 architecture and monopoly by designing a new CPU (and Processor block). 

Why do we do it?

The world needs a lower CO2 footprint. Data centers consume the energy equivalent of all air traffic globally, or about 200 TWh yearly and increasing. 

According to all independent sources, more energy-efficient CPUs are the only solution to making a real impact in reducing CO2 footprint in data centers. 

Who are we?

We are a team of engineers located in Oslo, Stavanger, and a (tiny) team in Trondheim. Ascenium is owned by Norwegian shareholders with a long track record of disruption in technology markets (and they have deep pockets and a long perspective).


Working at Ascenium

At Ascenium, we believe the best way to get good work done is to hire great people, set clear priorities, and then get out of people’s way to allow them to do their jobs in the way they think is best. We think it makes sense from a business perspective, but find that engineers also like this approach.


This is how we make it work:

  • Hire people who are not only technically excellent but also great collaborators and communicators.

  • Set clear priorities. The overall direction is communicated clearly by management, but how to get there is up to the engineers.

  • The best people to decide how to get a task done are the people working on it. And the best people to know which tasks to work on in the first place are the people who will be doing them. So allow engineers a lot of freedom in these regards.

  • Avoid all overhead. Flat organization, very few meetings, no Scrum, no backlog grooming meetings, etc. The entire engineering backlog currently has 46 issues.    

  • No estimates. We know estimates are mostly wrong anyway, so we don’t waste time on them. Instead, we make automatic projections based on the number of issues closed.

  • Encourage direct collaboration: ad hoc whiteboarding, online discussions, and pair design/programming trump meetings.

  • Give everyone the tools they need — private offices, 32 CPU cores, multiple or ultra-wide monitors, pick your own peripherals, etc.

  • Invest in the developer experience. We have a fast CI with good coverage and invest in scripts and tools to improve our efficiency. Pull requests are reviewed quickly.

  • Prioritize work-life balance, fostering a healthy and sustainable work environment.


Is it possible?

Is it even possible to compete with Intel, you might ask? Hard? Yes! Worthwhile things often are. Can it be done? Absolutely! Intel designed the x86 architecture 5 decades ago and in principle, hasn’t been able to improve the key characteristic of power consumption despite shrinking process nodes and increasing clock frequency in the CPU domain. 

Intel achieves its current performance with a massively complex out-of-order CPU architecture that consumes high amounts of energy. New chips do not improve performance, quite the contrary. Other disruptors base their designs on ARM RISC and RISC-V, but they are not materially different from x86. The instruction set doesn’t matter, they are all out-of-order RISC CPUs at the heart.

Data center applications are focused on Integer Performance, which is Ascenium's focus.

What does the core technology look like?

We are designing a new processor and the tools to build and use the processor. This includes:

  • Compiler 

    • We use LLVM and implement our own backend

  • CPU

    • Simulator implemented in C++

    • RTL/Verilog. We use a range of tools but particularly prefer open-source EDA tools during R&D phase.

We benchmark ourselves and our technology using industry-standard benchmarks:

  • EEMBC CoreMark

  • SPECInt2017: This is the defacto, industry-standard benchmark for data center chips


What competencies do we have?


  • Compiler development (LLVM)

  • RTL, using Chisel

  • EDA tooling: synthesis, floorplan, place, route. No detailed power and physical concerns at this point.


Which tools do we use?


  • C++ development in the space of LLVM backend, as well as simulation. We like to use the latest compilers, as well as tools like clang-tidy, clang-format, etc.

  • Python & various scripting for CI and utilities

  • Chisel, a DSL based on Scala that utilizes functional programming concepts as well as procedural programming to generate RTL (Verilog)

  • OpenROAD for flushing out major issues in the RTL and having quantitative data-driven feedback

  • Open source, extensively. This includes engaging with the community. .. and we are transitioning to commercial PDK and EDA tools as our technology is maturing

  • Google Workspace, github, etc also in use.

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