THE ASCENIUM DIFFERENCE
Current general purpose processor architectures are based on a 50-year-old design approach using the ISA (Instruction Set Architecture) as an API (Application Programming Interface) between the compiler and the hardware. This approach that has run out of gas despite ever more exotic and expensive optimization attempts. Whether the architecture is based on MIPS, or ARM, or Power, or RISC-v, or x86 - they are all basically the same at the low level pipeline hardware level.
But compilers can now do much more . . .
What is needed is a faster core building block . . .
. . . a faster leaner compute engine, that leverages a new approach for compiling programs. This leaner faster general purpose compute engine - which we call Aptos - then becomes the basic building block for higher performance energy efficient datacenter compute solutions.
The Datacenter Energy Challenge and Compute Disaggregation Opportunity
The exponential influx of data (video, audio, sensor) accelerated by Deep Learning and 5G only increases the importance of compute efficiency for energy management, and also means “compute must be brought to the data” in the datacenter
This disaggregation of compute resources creates opportunities for new general purpose processor architectures in the datacenter – Users want to program in C/C++, not CUDA, OpenCL or Verilog! Compute efficiency – the optimal utilization of ALL the datacenter resources – is key to minimizing datacenter energy usage.
* Google datacenter
* Partha Ranganathan (Google) et. al., The Datacenter as a Computer, 3rd ed, Morgan Claypool, 2019
Time To think Outside the Box!
Ascenium introduces compiler advances that allow the compiler to do much more of the work extracting performance – enabling a fresh “re‐think” of the traditional deep pipeline processor design approach to a simpler, faster, and more efficient architecture. This enables Ascenium to eliminate the complexity, area, and energy cost of the deep pipeline and other complex run-time approaches such as speculation, Out-of-Order execution, and renaming and to adopt a simpler parallel multi-dimensional approach directly controlled by the compiler.
Data Center Opportunities
Opportunities for higher performance general purpose processors exist in the Core, Aggregation, and Access Layers as shown below: