Ascenium will disrupt existing datacenter computing with a much higher performance solution that takes a completely different "out of box" approach to general purpose processor architecture.
Energy costs in the datacenter dominate TCO (Total Cost of Ownership). Processors consume~60% of all power in Google data centers.1 Efficient utilization of computing resources, which drive overall utilization efficiency, is a top priority for the data center industry. "Utilization drives TCO".2
The amount of data pouring into the data center continues to grow exponentially, and the size of applications executed by datacenter processors is also rapidly growing ‐ putting huge pressure on available computing resources.
New embarrassingly parallel workloads such as Deep Learning training are best served by purpose-built architectures, predominantly GPU. But these purpose-built GPUs and ASICs are not "general purpose CPUs" that are easily programmed in C++, which is by far the dominant language of code
executing in the datacenter.
Most computing in the data center is still handled by Host x86 CPUs (i.e. Xeon) that are comprised of many‐core configurations of single core architectures such as SkyLake.
Instruction driven single threaded deeply pipelined CPU cores are the basis for all general purpose processor architectures (including SkyLake), however single thread CPU performance gains stalled 15 years ago, and is one of the reasons architects have been forced to multi‐core chips.
Ascenium has "thought outside the box" to crack the processor performance barrier. Rather than heroically attempting to elevate an alternate instruction driven deeply pipelined architecture (e.g. ARM) to the task, Ascenium bypasses existing architectural limitations by eliminating both the instruction driven model and the deep pipeline. Ascenium leverages the compiler to do much more of the work, allowing the run time hardware can be greatly simplified. To accomplish this disruptive approach, Ascenium leverages new compiler advances based on SAT (SATisfiability) solvers.
The Ascenium Aptos then is a general purpose processor without an instruction set ‐ the
first of a new class of Software Defined Processors ‐ programmed in standard High Level
Languages such as C/C++. Ascenium expects a single Aptos processor core to achieve a 5x performance gain over existing single-threaded deeply pipelined single CPU cores.
However, industry insiders insist the TCO ROI
is so high for improved compute efficiency in the datacenter (primarily due to energy cost savings),that a 30% improvement on SPECint benchmarks in single threaded single core performance overx86 is sufficient to break into the market.